Microelectronic devices have become prevalent in all aspects of electronic circuits, and the design of transistors used in such circuits typically takes into account various factors including layout area, power consumption, speed, and the like. Various computer-assisted design systems have arisen and many of these systems attempt to consider and optimize the above factors in developing circuit designs. The aim of these systems is to increase the efficiency of circuit design, and the systems themselves are periodically improved which may therefore also improve the circuit designs resulting from the system.
The increasing demand of electronic devices is driving the need to design circuits that provide increasingly higher transistor performance at low standby power. Moreover, as technology scales shrink, minimizing the leakage current associated with an increasing number of smaller-dimensioned memory transistors is expected to become increasingly important. The tradeoff between transistor leakage and drivability, however, limits the performance of conventional low-power technologies. Current conventional transistor design methodologies fail to address these concerns.
Accordingly, what is needed in the art is a transistor design methodology to optimize power management that reduces standby leakage current while maintaining high performance requirements.